This invention relates to the testing of semiconductor devices, and particularly to the parallel testing of multiple semiconductor devices, for example, on a wafer. Semiconductor devices are manufactured in the form of wafers comprising multiple devices. A typical wafer may contain many thousands of devices. The wafers are diced into individual dies for final packaging.
Testing of devices is often performed prior to dicing of the wafer as it is convenient to handle a single wafer rather than individual dies to perform the testing. Devices may also be tested after packaging.
Testing is performed using Automated Test Equipment (ATE) which, together with a Device Handler or Wafer Prober, makes contact with each device to be tested and performs the required tests. Contact with the device may be achieved by probes or pins on a test head or a socket contacting pads or balls on devices. Practical considerations restrict testing to one or a very small subset of the devices on a wafer simultaneously. Current ATE has sufficient resources (power supplies, signal sources, data acquisition channels) to test 8 or 16 devices at a time. The ATE makes contacts with devices in turn, typically moving the wafer, to sequentially test each device (or the subset selected for test) in turn.
ATE generally provides a standard set of sources and measurement systems which are interfaced to a particular device under test using a probe card. Such a system allows the use of standard ATE for testing multiple device designs without requiring redesign of the whole system. Probe cards are interfaces boards that connect between the standard ATE connections and the particular inputs and outputs of the devices under test.
The resources of the ATE can be configured for use in the manner that best suits the particular devices under test. This is achieved by specific design of the probe card and software to control the operation of the ATE. The resources may be utilized to test each device, or a subset thereof, contacted by the probe card (typically 8 or 16) simultaneously. Testing time is therefore reduced for a given number of devices on a wafer. The number of devices that can be tested in parallel is limited by the resources of the ATE. Increasing the resources available in ATE is generally extremely expensive and may not provide a cost-efficient route to improving test times.
Testing time can be reduced by performing two or more tests concurrently on each device. For example, it may be possible to perform RF testing at the same time as digital testing. However, the number of tests that can be performed in parallel is limited by conflicting resources in the devices thereby limiting the reduction in test time.
There is therefore a requirement for a test system to reduce test times without requiring additional resources from the ATE.